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ccm-pfc ICE3PCS03G standalone power factor correction (pfc) controller in continuous conduction mode (ccm) version 2.0, 5 may 2010 power management & supply
edition 2010-05-12 published by infineon technologies ag 81726 munich, germany ?infineon technologies ag 05/05/10. all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical valu es stated herein and/or any information regarding the application of the device, infineon technologies her eby disclaims any and all warranties and liabilities of any kind, including wi thout limitation, warranties of non-infrin gement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the near est infineon technologies office. infineon technologies components may be used in life-supp ort devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ccm-pfc revision history: datasheet
ccm-pfc ICE3PCS03G version 2.0 3 5 may 2010 type package ICE3PCS03G pg-dso-8 standalone power factor correction (pfc) controller in continuous conduction mode (ccm) ICE3PCS03G pg-dso-8 product highlights ? high efficiency over the whole load range ? lowest count of external components ? accurate and adjustable switching frequency ? integrated digital voltage loop compensation ? fast output dynamic response during load jump ? external synchronization ? low peak current limitation features ? continuous current operation mode pfc ? wide input range of vcc up to 25v ? enhanced dynamic response without input current distortion ? accurate brown-out protection threshold ? external current loop compensation for greater user flexibility ? open loop protection ? maximum duty cycle of 95% (typical) description the ICE3PCS03G is a 8-pins wide input range controller ic for active power factor co rrection converters. it is de- signed for converters in boost topology, and requires few external components. its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the ic. 90 ~ 270 vac line filter c e l bo os t r sh u n t r gate d byp d b r cs c b r bvs 2 r bvs 3 r bvs 1 r gs bop isense gate d br o1 d br o2 r freq c ic o mp c vc c v c c gnd vcc icomp freq vsense r br o2 r br o1 r br o3 c br o
ccm-pfc ICE3PCS03G version 2.0 4 5 may 2010 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 frequency setting and external synchronization . . . . . . . . . . . . . . . . . . . . . 8 3.4.1 frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.2 external synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 voltage loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5.1 notch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5.2 voltage loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 average current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.1 complete current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.2 current loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.3 pulse width modulation (pw m) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 pwm logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 system protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8.1 input voltage browno ut protection(bop) . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8.2 peak current limit (pcl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8.3 open loop protection (olp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8.4 first over-voltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9 output gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.10 protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.2 variable frequency section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.4 external synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.5 pfc brownout protection section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.6 system protection section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.7 current loop section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.8 voltage loop section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.9 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.10 gate drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
version 2.0 5 5 may 2010 ccm-pfc ICE3PCS03G pin configurati on and functionality 1 pin configuration and functionality 1.1 pin configuration figure 1 pin configuration (top view) 1.2 pin functionality isense (current sense input) the isense pin senses the voltage drop at the external sense resistor (r shunt ). this is the input signal for the average current regulation in the current loop. it is also fed to the peak current limitation block. during power up time, high inrush currents cause high negative voltage drop at r shunt , driving currents out of pin 1 which could be beyond the absolute maximum ratings. therefore a series resistor (r cs ) of around 50 ? is recommended in order to limit this current into the ic gnd (ic ground) the ground potential of the ic. icomp (current loop compensation) low pass filter and compensation of the current control loop. the capacitor which is connected at this pin integrates the output curren t of ota6 and averages the current sense signal. freq (frequency setting) this pin allows the setting of the operating switching frequency by connecting a resistor to ground. the frequency range is from 21khz to 250khz. bop (brownout protection) bop monitors the ac input voltage for brownout protection. vsense vsense is connected via a resistive divider to the bulk voltage. the voltage of vsense relative to gnd represents the output volt age. the bulk voltage is monitored for voltage regulation, over voltage protection and open loop protection. vcc vcc provides the power supply of the ground related to ic section. gate gate is the output for driving the pfc mosfet.its gate drive voltage is clamped at 15v (typically). pin symbol function 1 isense current sense input 2 gnd ic ground 3 icomp current loop compensation 4 freq switching frequency setting 5 bop brownout protection 6 vsense bulk voltage sense 7 vcc ic supply voltage 8 gate gate drive vsense isense bop freq icomp p-dso-8 gate gnd vcc package pg-dso-8
ccm-pfc ICE3PCS03G block diagram version 2.0 6 5 may 2010 2 block diagram a functional block diagram is given in figure 2. note that the figure only shows the brief functional block and does not represent the implementation of the ic. figure 2 block diagram brownout protection oscillator/ synchronization current loop compensation/ pcl vcc unit protection unit voltage loop compensation ramp generator pwm logic driver nonlinear gain ICE3PCS03G c e l boost d by p d b c b r bvs2 r bvs3 r bvs1 d br o1 d bro2 q b r cs r shunt r ga te r bro1 r bro2 r bro3 c ic om p 90 ~ 270 vac line filter r freq c bro auxiliary supply freq gate bop vcc vsense isense icomp gnd c isense
ccm-pfc ICE3PCS03G block diagram version 2.0 7 5 may 2010 table 1 bill of material component parameters rectifier bridge gbu8j c e 100nf/x2/275v l boost 750uh q b ipp60r199cp d byp mur360 d b idt04s60c c b 220f/450v d bro1...2 1n4007 r bro1...2 3.9m ? r bro3 130k ? c bro 3 f r shunt 60m ? c isense 1nf r cs 50 ? r gate 3.3 ? r freq 67k ? c icomp 4.7nf/25v r bvs1...2 1.5m ? r bvs3 18.85k ?
ccm-pfc ICE3PCS03G functional description version 2.0 8 5 may 2010 3 functional description 3.1 general the ICE3PCS03G is a 8-pins control ic for power factor correction converters. it is suitable for wide range line input applications from 85 to 265 vac with overall efficiency above 90%. the ic supports converters in boost topology and it operates in continuous conduction mode (ccm) with average current control. the ic operates with a cascaded control; the inner current loop and the outer voltage loop. the inner current loop of the ic contro ls the sinusoidal profile for the average input current. it uses the dependency of the pwm duty cycle on the line input voltage to determine the corresponding input current. this means the average input current fo llows the input voltage as long as the device operates in ccm. under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (dcm) resulting in a higher harmonics but still meeting the class d requirement of iec 1000-3-2. the outer voltage loop controls the output bulk voltage, integrated digitally within the ic. depending on the load condition, internal pi compen sation output is converted to an appropriate dc voltage which controls the amplitude of the average input current. the ic is equipped with various protection features to ensure safe operating condition for both the system and device. 3.2 power supply an internal under voltage lockout (uvlo) block monitors the vcc power supply. as soon as it exceeds 12.0v and both voltages at pin 6 (vsense) >0.5v and pin 5 (bop) >1.25v, the ic begins operating its gate drive and performs its star tup as shown in figure 3. if vcc drops below 11v, the ic is off. the ic will then be consuming typically 1.4ma, whereas consuming 6.4ma during normal operation the ic can be turned off and forced into standby mode by pulling down the voltage at pin 6 (vsense) below 0.5v. figure 3 state of operat ion respect to vcc 3.3 start-up during power up when the vout is less than 95% of the rated level, internal voltage loop output increases from initial voltage under the soft-st art control. this results in a controlled linear increase of the input current from 0a thus reducing the stress in the external components. once vout has reached 95% of the rated level, the soft- start control is released to achieve good regulation and dynamic response. 3.4 frequency setting and external synchronization the ic can provide external switching frequency setting by an external resistor r freq and the online synchronization by external pulse signal at freq pin. 3.4.1 frequency setting the switching frequency of the pfc converter can be set with an external resistor r freq at freq pin as shown figure 2. the pin voltage at v freq is typical 1v. the corresponding capacitor for the oscillator is integrated in the device and the r freq /frequency is given in figure 4. the recommended operating frequency range is from 21khz to 250khz. as an example, a r freq of 67k ? at pin freq will set a switching frequency f sw of 65khz typically. uvlo bulk voltage rises to 95% rated value within 200ms v bulk v cc i vcc 20% 95% 100% 12v 1.4ma <6.4ma with 1nf external cap. at gate drive pin 26v 3.5ma normal operation standby mode (v vsense < 0.5v)
ccm-pfc ICE3PCS03G functional description version 2.0 9 5 may 2010 figure 4 frequency versus r freq 3.4.2 external synchronization the switching frequency can be synchronized to the external pulse signal after 6 external pulses delay once the voltage at the freq pin is higher than 2.5v. the synchronization means two points. firstly, the pfc switching frequency is tracking the external pulse signal frequency. secondly, the falling edge of the pfc signal is triggered by the rising edge of the external pulse signal. figure 5 shows the blocks of frequency setting and synchronization. the external r syn combined with r freq and the external diode d syn can ensure pin voltage to be kept between 1.0v (clamped externally) and 5v (maximum pin voltage). if the external pulse signal ha s disappeared longer than 108 s (typical) the switching frequency will be synchronized to internal clock set by the external resistor r freq . figure 5 frequency setting and synchronization 3.5 voltage loop the voltage loop is the outer loop of the cascaded control scheme which controls the pfc output bus voltage v out . this loop is closed by the feedback sensing voltage at vsense which is a resistive divider tapping from v out . the pin vsense is the input of sigma-delta adc which has an internal reference of 2.5v and sampling rate of 3.55khz (typical). the voltage loop compensation is integrated digitally for better dynamic response and saving design effort. figure 6 shows the important blocks of this voltage loop. figure 6 voltage loop 3.5.1 notch filter in the pfc converter, an averaged current through the output diode of rectified sine waveform charges the output capacitor and results in a ripple voltage at the output capacitor with a fre quency two times of the line frequency. in this digital pfc, a notch filter is used to remove the ripple of the sensed output voltage while keeping the rest of the signal almost uninfluenced. in this way, an accurate and fast output voltage regulation without influence of the output voltage ripple is achieved. 3.5.2 voltage loop compensation the proportion-int egration (pi) compensation of the voltage loop is integrated digitally inside the ic. the digital data out of the pi compensator is converted to analog voltage for current loop control. frequency vs resistance 0 20 40 60 80 100 120 140 160 180 200 220 240 260 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 resistance/kohm frequency/khz 19.2 232 43 100 20.2 221 49 90 21.2 210 55 80 23 200 62 70 25 191 74 60 26.2 169 86 50 29.5 150 106 40 31.5 140 141 30 34 130 211 20 36 120 249 17 40 110 278 15 frequency /khz resistance /kohm frequency /khz resistance /kohm r freq d syn ota 7 c9 r syn freq 1. 0v 2.5v/1.25v syn . clock i osc syn vsense gate driver gate v in av(i in ) nonlinear gain current loop + pwm generation t sigma- delta adc notch filter pi filter 2.5v rectified input voltage d b c b r bvs2 r bvs3 r bvs1 l boost q b r gate c2 a c1 a c1 b r s q q ovp ovp olp 0.5v 2.5v 2.7 v 500 ns
ccm-pfc ICE3PCS03G functional description version 2.0 10 5 may 2010 the nonlinear gain block controls the amplitude of the regulated inductor current. the input of this block is the output voltage of integrated pi compensator. this block has been designed to reduce the voltage loop dependency on the input voltage in order to support the wide input voltage range (85vac-265vac). figure 7 gives the relative output power transfer curve versus the digital word from the integrated pi compensator. the output power at the input voltage of 85vac and maximum digital word of 256 from pi compensator is set as the normative power and the power curves at different input voltage present the relative power to the normative one. figure 7 power transfer curve 3.6 average current control the choke current is sensed through the voltage across the shunt resistor and averaged by the icomp pin capacitor so that the ic can control the choke current to track the instant va riation of the input voltage. 3.6.1 complete current loop the complete system current loop is shown in figure 8. it consists of the current loop block which averages the voltage at isense pin resulted from the inductor current flowing across r shunt . the averaged waveform is compared with an internal ramp in the ramp generator and pwm block. on ce the ramp crosses the average waveform, the comparator c10 turns on the driver stage through the pwm logic block. the nonlinear gain block defines the amplitude of the inductor current. the followi ng sections describe the functionality of each individual blocks. figure 8 complete system current loop 3.6.2 current loop compensation the compensation of the curr ent loop is implemented at the icomp pin. this is ota6 output and a capacitor c icomp has to be installed at this node to ground (see figure 8). under normal mode of the operation, this pin gives a voltage which is pr oportional to the averaged inductor current. this pin is internally shorted to 5v in the event of standby mode. 3.6.3 pulse width modulation (pwm) the ic employs an average current control scheme in continuous mode (ccm) to achieve the power factor correction. assuming the voltage loop is working and output voltage is kept constant, the off duty cycle d off for a ccm pfc system is given as: d off =v in /v out from the above equation, d off is proportional to v in . the objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle d off , and thus to the input voltage v in . figure 9 shows the scheme to achieve the objective. 0.00001 0.00010 0.00100 0.01000 0.10000 1.00000 10.00000 0 18 37 55 73 91 110 128 146 165 183 201 219 238 256 pi digital output relative output power power at 85v power at 265v rectified input voltage d b c b l boost q b r gate r shunt r cs r s gate driver gate ota6 icomp 5v current loop compensation current loop nonlinear gain 5.0ms +/ -50ua (linear range) c icomp s2 fault isense c10 pwm comparator pwm logic q input from voltage loo p voltage proportional to averaged inductor current
ccm-pfc ICE3PCS03G functional description version 2.0 11 5 may 2010 figure 9 average current control in ccm the pwm is performed by the intersection of a ramp signal with the averaged inductor current at pin 3 (icomp). the pwm cycles starts with the gate turn off for a duration of t offmin (600ns typ.) and the ramp is kept discharged. the ramp is allowed to rise after the t offmin expires. the off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. this results in the proportional relationship be tween the average current and the off duty cycle d off . figure 10 shows the timing diagrams of the t offmin and the gate waveforms. figure 10 ramp and pwm waveforms 3.7 pwm logic the pwm logic block prioritizes the control input signal and generates the final logic signal to turn on the driver stage. the speed of the logic gates in this block, together with the width of the reset pulse t offmin , are designed to meet a maximum duty cycle d max of 95% at the gate output under 65khz of operation. in case of high input currents which results in peak current limitation, the gate will be turned off immediately and maintained in off state for the current pwm cycle. the signal t offmin resets (highest priority, overriding other i nput signals) both the current limit latch and the pwm on latch as illustrated in figure 11. figure 11 pwm logic 3.8 system protection the ic provides numerous pr otection features in order to ensure the pfc system in safe operation. 3.8.1 input voltage brownout protection(bop) brownout occurs when the input voltage v in falls below the minimum input voltage of the design (i.e. 85v for universal input voltage range) and the v cc has not entered into the v ccuvlo level yet. for a system without bop, the boost converter wi ll increasingly draw a higher current from the main s at a given output power which may exceed the maximum design values of the input current. ICE3PCS03G provides a new bop feature whereby it senses directly the input voltage for input brown-out condition via an external resistor/capacitor/diode network shown in figure 12. this network provides a filtered value of vin which turns the ic on when the voltage at pin 5 (bop) is more than 1.25v. the ic enters into the fault mode when bop goes below 1.0v. the hysteresis prevents the system to oscillate between normal and fault mode. note also that the peak of vin needs to be at least 20% of the rated v out in order to overcome olp and powerup system. ramp profile ave(i in ) at icomp gate drive t t pwm cycle ramp released t off_min 600 ns clock v c,ref (1 ) v ramp gate (1) v c,ref is a function of v ic omp r s q q current limit latch r s q q pwm on latch high = turn on gate t off_min 600 ns peak current limit current loop pw m on signal
ccm-pfc ICE3PCS03G functional description version 2.0 12 5 may 2010 figure 12 input brownout protection 3.8.2 peak current limit (pcl) the ic provides a cycle by cycle peak current limitation (pcl). it is active when the voltage at pin 1 (isense) reaches -0.4v. this voltage is amplified by a factor of - 2.5 and connected to comparator with a reference voltage of 1.0v as shown in figure 13. a deglitcher with 200ns after the comparator improves noise immunity to the activation of this protection. figure 13 peak current limit (pcl) 3.8.3 open loop protection (olp) whenever vsense voltage falls below 0.5v, or equivalently v out falls below 20% of its rated value, it indicates an open loop condition (i.e. vsense pin not connected) or an insufficient input voltage v in for normal operation. it is implemented using comparator c2a with a threshold of 0.5v as shown in the ic block diagram in figure 6. 3.8.4 first over-voltage protection (ovp) whenever v out exceeds the rated value by 8%, the over-voltage protection ovp1 is active as shown in figure 6. this is implemented by sensing the voltage at vsense pin with respect to a reference voltage of 2.7v. a vsense voltage higher than 2.7v will immediately turn off the gate, thereby preventing damage to bus capacitor. after bulk voltage falls below the rated value, gate drive resumes switching again. 3.9 output gate driver the output gate driver is a fa st totem pole gate drive. it has an in-built cross conduction currents protection and a zener diode z1 (see figure 14) to protect the external transistor switch against undesirable over voltages. the maximum voltage at pin 8 (gate) is typically clamped at 15v. the output is active high and at vcc voltages below the under voltage lockout threshold v ccuvlo , the gate drive is internally pull low to maintain the off state. figure 14 gate driver line filter d bro1 d bro2 r bro1 r bro2 r bro3 90 ~ 270 vac c bro bop c8b c8a r s q q br ownout latch 1.25 v 1v brownout r shunt r cs full-wave rectifier isense ao2 c5 200ns sgnd g=-2.5 1v i in pcl external mos gate z1 vcc gate driver pwm logic high to turn on lv * lv: level shift reg (17 v )
ccm-pfc ICE3PCS03G functional description version 2.0 13 5 may 2010 3.10 protection function description of fault fault-type min. duration of effect consequence voltage at pin isense < -400mv pcl 200 ns gate driver is turned off immediately during current switching cycle voltage at pin bop < 1v bop 20 s gate driver is turned o ff. soft-restart after bop voltage > 1.25v voltage at pin vsense < 0.5v olp 1 s power down. soft-restart after vsense voltage > 0.5v voltage at pin vsense > 108% of rated level ovp1 12 s gate driver is turned off until vsense voltage < 2.5v.
ccm-pfc ICE3PCS03G electrical characteristics version 2.0 14 5 may 2010 4 electrical characteristics all voltages are measured with respect to ground (pin 2). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reas on make sure, that any capacitor t hat will be connected to pin 7 (vcc) is discharged before assembling the application circuit. parameter symbol values unit note / test condition min. typ. max. vcc supply voltage v vcc -0.3 26 v gate voltage v gate -0.3 17 v clamped at 15v if driven internally. isense voltage v isense -20 5.3 v 1) 1) absolute isense current should not be exceeded isense current i isense -1 1 ma vsense voltage v vsense -0.3 5.3 v vsense current i vsense -1 1 ma icomp voltage v icomp -0.3 5.3 v freq voltage v freq -0.3 5.3 v bop voltage v bop -0.3 9.5 v 2) 2) absolute bop current should not be exceeded bop current i bop -1 35 a junction temperature t j -40 150 c storage temperature t a,sto -55 150 c thermal resistance r thja 185 k/w junction to air soldering temperature t sld 260 c wave soldering 3) 3) according to jesd22a111 esd capability v esd 2 kv human body model 4) 4) according to eia/jesd22-a114-b (dischar ging an 100 pf capacitor through an 1.5k ? series resistor)
ccm-pfc ICE3PCS03G electrical characteristics version 2.0 15 5 may 2010 4.2 operating range note: within the operati ng range the ic operates as described in the functional description. 4.3 characteristics note: the electrical characteristics involve the spread of values given within the sp ecified supply voltage and junction temperature range t j from -25 c to 125 c. typical values represent the median values, which are related to 25 c. if not othe rwise stated, a supply voltage of v vcc = 18v, a typical switching frequency of f freq =65khz are assumed and the ic op erates in active mode. furthermore, all voltages are referring to gnd if not otherwise mentioned. 4.3.1 supply section parameter symbol values unit note / test condition min. typ. max. vcc supply voltage @ 25c v vcc v vcc,off 25 v t j =25c junction temperature t j -25 125 c pfc switching frequency f pfc 21 250 khz parameter symbol limit values unit note/test condition min. typ. max. vcc turn-on threshold v ccon 11.5 12 12.9 v vcc turn-off threshold/ under voltage lock out v ccuvlo 10.5 11.0 11.9 v vcc turn-on/off hysteresis v cchy 0.7 1 1.45 v start up current before v ccon i ccstart1 - 380 680 av ccon -1.2v start up current before v ccon i ccstart2 -1.42.4mav ccon -0.2v operating current with active gate i cchg -6.48.5mac l = 1nf operating current during standby i ccstdby -3.54.7mav vsense = 0.4v v icomp = 4v
ccm-pfc ICE3PCS03G electrical characteristics version 2.0 16 5 may 2010 4.3.2 variable frequency section 4.3.3 pwm section 4.3.4 external synchronization parameter symbol limit values unit test condition min. typ. max. switching frequency (typical) f swnom 62.5 65 67.5 khz r5 = 67k ? switching frequency (min.) f swmin - 21 - khz r5 = 212k ? switching frequency (max.) f swmax - 250 - khz r5 = 17k ? voltage at freq pin v freq -1-v max. duty cycle dmax 93 95 98.5 % f sw =f swnom (r fre =67k ? ) parameter symbol limit values unit test condition min. typ. max. min. duty cycle d min 0%v vsense = 2.5v v icomp = 4.3v min. off time t offmin 310 600 920 ns v vsense = 2.5v v isense = 0v (r5 = 67k ? ) parameter symbol values unit note / test condition min. typ. max. detection threshold of external clock v thr_ext 2.5 v synchronization range f ext_range 50 150 khz synchronization frequency ratio f ext :f pfc 1:1 propagation delay from rising edge of external clock to falling edge of pfc gate drive t ext2gate 500 ns f ext =65khz allowable external duty on time t d_on 10 70 %
ccm-pfc ICE3PCS03G electrical characteristics version 2.0 17 5 may 2010 4.3.5 pfc brownout protection section 4.3.6 system protection section 4.3.7 current loop section parameter symbol values unit note / test condition min. typ. max. input brownout protection high to low threshold v bop_h2l 0.98 1 1.02 v input brownout protection low to high threshold v bop_l2h 1.21.251.3 v blanking time for bop turn_on t bopon 20 s input brownout protection bop bias current i bop -0.5 - 0.5 av bop =1.25v parameter symbol values unit note / test condition min. typ. max. over voltage protection (ovp) low to high v ovp1_l2h 2.65 2.7 2.77 v 108%v bulkrated over voltage protection (ovp) high to low v ovp1_h2l 2.45 2.5 2.55 v over voltage protection (ovp ) hysteresis v ovp1_hys 150 200 270 mv blanking time for ovp t ovp1 12 s peak current limitation (pcl) isense threshold v pcl -365 -400 -435 mv blanking time for pcl turn_on t pclon 200 ns parameter symbol values unit note / test condition min. typ. max . ota6 transconductance gain gm ota6 3.5 5.0 6.35 ms at temp = 25c ota6 output linear range 1) 1) the parameter is not subject to production test - verified by de sign/characterization i ota6 50 a icomp voltage during olp v icompf 4.8 5.0 5.2 v v vsense = 0.4v
ccm-pfc ICE3PCS03G electrical characteristics version 2.0 18 5 may 2010 4.3.8 voltage loop section 4.3.9 driver section 4.3.10 gate drive section parameter symbol values unit note / test condition min. typ. max . trimmed reference voltage v vsref 2.47 2.5 2.53 v 1.2% open loop protection (olp) vsense threshold v vs_olp 0.45 0.5 0.55 v vsense input bias current i vsense -1 - 1 a v vsense = 2.5v parameter symbol values unit note / test condition min. typ. max. gate low voltage v gatel --1.2vv cc =10v i gate = 5 ma -0.4-vi gate = 0 a --1.4v i gate = 20 ma -0.2 0.8 - v i gate = -20 ma gate high voltage v gateh -15-v v cc = 25v c l = 1nf - 12.4 - v v cc = 15v c l = 1nf 8.0 - - v v cc = v vccoff + 0.2v c l = 1nf parameter symbol values unit note / test condition min. typ. max. gate rise time t r -30-ns v gate = 20% - 80% v gateh c l = 1nf gate fall time t f -25-ns v gate = 80% - 20% v gateh c l = 1nf
ccm-pfc ICE3PCS03G outline dimension version 2.0 19 5 may 2010 5 outline dimension pg-dso-8 outline dimension notes: 1. you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . 2. dimensions in mm. does not include plastic or metal protrusion of 0.15 max. per sid e -0.05 -0.2 +0.1 5 0.41 i ndex marking (chamfer) x8 1 1) 4 8 1.27 5 a 0.1 0.2 m a (1.5) 0.1 min. 1.75 max. c c 6 ?.2 0.64 0.33 4 -0.2 -0.0 1 0.2 +0.05 x 45? ?.08 1) ?.25 max. 8? 1 ) i ndex m arking
qualit?t hat fr uns eine umfassende bedeutung. wir wollen allen ihren ansprchen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstrengungen gelten gleicherma?en der lieferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total quality im denken und handeln gegenber kollegen, lieferanten und ihnen, unserem kunden. unsere leitlinie ist jede aufgabe mit ?null fehlern? zu l?sen ? in offener sichtweise auch ber den eigenen arbeitsplatz hinaus ? und uns st?ndig zu verbessern. unternehmensweit orientieren wir uns dabei auch an ?top? (time optimized processes), um ihnen durch gr??ere schnelligkeit den entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns die chance, hohe leistung durch umfassende qualit?t zu beweisen. wir werden sie berzeugen. quality takes on an allencompassing significance at semiconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total quality in thought and deed, towards co-workers, suppliers and you, our customer. our guideline is ?do everything with zero defects?, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), greater speed on our part to give you that decisive competitive edge. give us the chance to prove the best of performance through the best of quality ? you will be convinced. http://www.infineon.com total quality management published by infineo n technologies ag

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